This invention relates to semiconductor wafer processing, and more particularly to semiconductor wafer level packaging.
In wafer level packaging processes, chips are packaged before singulation. These processes are presently limited to fan-in packaging, i.e. all packaging elements of a chip must fall within the shadow of the chip. Any elements formed outside the shadow of the chip are not supported and are destroyed upon singulation of the chip. The requirement that packaging elements fall within the chip""s shadow presents a challenge as device geometries shrink.
The use of an interposer board between a chip and a printed circuit board enables one to fan out interconnections beyond a chip""s edge. A chip is connected to the interposer board with connection in the chip""s shadow, and the interposer board and out the connections to the desired pitch. The interposer board, however, adds a level of complexity, thereby reducing reliability and increasing costs. The interposer board also adds bulk to the placement of a chip on a printed circuit board.
Equipment for wafer-level burn-in of semiconductor devices, i.e. testing of devices under heat for extended periods of time, needs to be robust enough with sufficient protection to handle large deviations between functioning and non-functioning devices.
In an aspect of the invention, a semiconductor structure comprises a semiconductor chip and a conductive layer disposed over a portion of the chip, the conductive layer having a portion that extends beyond an edge of the chip.
Embodiments can include the following. The conductive layer comprises a metal line. The chip comprises a device. The device comprises an integrated circuit. The device comprises a micro-electromechanical device. The semiconductor structure also includes a contact pad disposed on a surface of the device, and a portion of the conductive layer is in electrical communication with the contact pad. The structure has a front layer, with a first portion disposed on a first surface of the semiconductor chip, and a second portion extending beyond the edge of the chip, the conductive layer being disposed on the front layer. The front layer is a dielectric layer. The front layer is compliant. The front layer includes a bump.
In another aspect of the invention, a semiconductor structure includes a semiconductor chip and a front layer. The front layer has a first portion disposed on a first surface of the semiconductor chip, and a second portion extending beyond an edge of the chip.
In another aspect of the invention, a method for making a semiconductor structure includes providing a semiconductor chip having a device formed thereon and forming a layer over a portion of the device, such that a portion of the layer extends beyond an outer edge of the device.
Embodiments can include the following. The layer is a conductive layer. A line is defined in the conductive layer. A front layer is formed, having a first portion disposed on a first surface of the device, and a second portion extending beyond the edge of the device, with the conductive layer being disposed on the front layer. The device is formed proximate a first surface of the chip, and an encapsulating layer is formed proximate a second surface of the chip, so that the portion of the front layer extends beyond the outer edge of the device extends over the encapsulating layer.
Another aspect of the invention includes a method for making a semiconductor structure by providing a plurality of semiconductor chips and forming a first encapsulating layer between each of the semiconductor chips, such that the encapsulating layer bonds the chips together. In some embodiments, a second encapsulating layer is formed over the backside of the chips.
An advantage of an aspect of the inventive concept is that wafer level packaging steps are carried out on substrates larger than the size of a commercially available semiconductor wafer. Typically, wafer level packaging is done with, e.g., silicon wafers having maximum diameters of 300 mm. Printing technology, however, is readily available for processing substrates with dimensions of up to 600 mm. Printing technology is, therefore, a cost-effective method for processing multiple chips simultaneously.
Another advantage of an aspect of the inventive concept is the possibility to singulate dies by cutting through only soft encapsulating material instead of hard silicon. The former procedure is faster and therefore cheaper than the latter.
Another advantage of an aspect of the inventive concept is that burn-in of devices can be carried out on a reconstituted wafer having only known good die. Burn-in equipment can, therefore, be less complex.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.